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[VHDL-FPGA-Verilog] top

Description: 脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[Other Embeded program] code

Description: 其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例-Two of the projects themselves to do: a tracking radar simulator is based on FPGA/CPLD
Platform: | Size: 6978560 | Author: 肖寒 | Hits:

[Graph Drawing] Untitled

Description: 自编的脉冲压缩雷达的MATLAB仿真程序-Self-pulse compression radar simulation program MATLAB
Platform: | Size: 1024 | Author: yuanshiji | Hits:

[VHDL-FPGA-Verilog] CICFPGA

Description: 本文总结了CIC 滤波器理论要点，介绍了采用FPGA设计CIC 滤波器的基本方法，使滤波器的参数可以按实际需要任意更改，给出了仿真结，验证了设计的可靠性和可行性。采用该方法设计的CIC 滤波器已用于DDC芯片，也适合下一代高频雷达系统的要求。-This paper summarizes the main points of CIC filter theory, introduced the CIC filter design using FPGA basic ways in which filter parameters can be arbitrary according to the actual needs change, the simulation node to verify the reliability of the design and feasibility. Designed using the CIC filter has been used in DDC chips, also suitable for the next generation of high-frequency radar system requirements.
Platform: | Size: 700416 | Author: 会飞的鱼 | Hits:

[VHDL-FPGA-Verilog] DUC

Description: 数字上变频DUC是与数字下变频ddc相对应的工作.目前实现方式主要有:专用芯片,通用DSP和FPGA实现三种.本程序即给出了XILINX公司的Digital Up Converter核心程序(IP CORE)以及响应的使用说明,对于从事雷达,无线通信的工程人员和研究者有很大用处.-DUC is a digital up-conversion and digital down conversion that corresponds to the work of ddc. Realize the current approach are: ASIC, DSP and FPGA generic realize three. This procedure is given that the company XILINX core Digital Up Converter program (IP CORE) and to respond to instructions, for radar, wireless communications, engineers and researchers have great usefulness.
Platform: | Size: 305152 | Author: 周严 | Hits:

[Audio program] continue_wave_radar

Description: 一个连续波雷达的VHDL实现程序，用VHDL编写，带有测试激励文件-A continuous-wave radar to achieve the VHDL program, using VHDL prepared a document with test incentives
Platform: | Size: 67584 | Author: HOULIANG | Hits:

[DSP program] sin

Description: CCS环境下，脉冲压缩雷达线性调频时域处理算法研究（包含整个项目）-CCS environment, linear frequency modulation pulse compression radar deal with time-domain algorithm (including the entire project)
Platform: | Size: 51200 | Author: zhangshuai | Hits:

[VHDL-FPGA-Verilog] FFT

Description: FFT的VHDL实现程序 希望对大家有用 -FFT of the VHDL program hope to achieve useful
Platform: | Size: 27648 | Author: cathy | Hits:

[Communication-Mobile] ps110

Description: bpsk信号调制，用于产生一种雷达信号。-BPSK signal modulation, used to generate a radar signal.
Platform: | Size: 1024 | Author: wang | Hits:

[SCM] source_code

Description: 一些源程序，主要包括CAN总线驱动、sdram VHDL实现、ucos2的移植、SDIO驱动、tcpip的实现、usb控制器代码、基于FPGA的雷达目标模拟器等-Some source code, including CAN bus driver, sdram VHDL implementation, ucos2 transplant, SDIO drivers, tcpip of implementation, usb controller code, based on the FPGA, such as radar target simulator
Platform: | Size: 6898688 | Author: 磊 | Hits:

[Software Engineering] sji

Description: 频率合成技术在现代电子技术中具有重要的地位。在通信、雷达和导航等设备中，它可以作为干扰信号发生器；在测试设备中，可作为标准信号源，因此频率合成器被人们称为许多电子系统的“心脏”。直接数字频率合成（DDS——Digital Direct Frequency Synthesis）技术是一种全新的频率合成方法，是频率合成技术的一次革命。本文主要分析了DDS的基本原理及其输出频谱特点，并采用VHDL语言在FPGA上实现。对于DDS的输出频谱，一个较大的缺点是：输出杂散较大。针对这一缺点本文使用了两个方法加以解决。首先是压缩ROM查找表，-Abstract；The frequency synthesis technology has the important status in the modern electronic technology. In equipment such as correspondence, radar and navigation, it may work as the unwanted signal generator In the test facility, may work as the standard signal source, therefore the frequency synthesizer is called by the people as "the heart" of many electronic systems .DDS——Digital Direct Frequency Synthesis technology is one brand-new frequency synthetic method, is a frequency synthesis technology revolution. This paper analyzes the basic principle of DDS and its output frequency spectrum characteristic, and realizes it with VHDL language on FPGA. In regard to the output
Platform: | Size: 961536 | Author: 番薯军 | Hits:

[Scanner] dsp_radar

Description: radar detecttion in verilog
Platform: | Size: 23552 | Author: kasmi | Hits:

[Software Engineering] HW4

Description: Radar Simulation in VHDL
Platform: | Size: 346112 | Author: Daniel R. | Hits:

[Other] a1

Description: 基于FPGA的多相滤波器设计 摘要: 以脉冲多普勒雷达信号处理为背景,研究了数字多相滤波器的特点和设计方法 进而研究数字多相滤波器的数字仿真 方法与 FPGA 实现技术 对于自主研究 设计和实现雷达信号处理的各种结构的滤波器具有重要的意义-Based FPGA multiphase Filter Design Abstract: Pulse Doppler signal processing background studied digital polyphase filter characteristics and design method then research digital multiphase filter Digital Simulation Method and FPGA Realization Technology For autonomous research design and realization radar signal processing various structures filter great significance
Platform: | Size: 322560 | Author: sfef | Hits:

[Other] a2

Description: 用MATLAB设计及FPGA实现IIR滤波器的方法 摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波 器，其阶数低，实时响应快，适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法，对于 四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。-Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.
Platform: | Size: 2021376 | Author: sfef | Hits:

[Software Engineering] juzhenqiuni_FPGA

Description: RMMSE雷达脉冲压缩快速算法中矩阵求逆的FPGA实现-RMMSE radar pulse compression fast algorithm for FPGA implementation matrix inversion
Platform: | Size: 366592 | Author: lq | Hits:

[VHDL-FPGA-Verilog] KNOWLEDGE-BASED

Description: radar book knoledge base
Platform: | Size: 4752384 | Author: jamshidi | Hits:

[VHDL-FPGA-Verilog] farrow

Description: 一份很好的数字时延程序（采用farrow算法），采用Verilog HDL，经过测试通过，是我一个雷达项目中的代替模拟时延的。精度很高，并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
Platform: | Size: 7234560 | Author: 左洪成 | Hits:

[VHDL-FPGA-Verilog] radar

Description: design of radar in VHDL programing
Platform: | Size: 844800 | Author: sri | Hits:

[VHDL-FPGA-Verilog] VHDL-radar

Description: 脉冲多普勒雷达回波信号相干积累的VHDL源程序-Coherent pulse Doppler radar echo signal accumulation VHDL source code ，it is easy to use
Platform: | Size: 2048 | Author: | Hits:
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